The present application relates to a semiconductor structure and a method of forming the same. More particularly, the present application relates to a fuse structure in which a portion of the neck region of the fuse structure is defined by a gap formed between a bottom III-V compound semiconductor material portion and a top III-V compound semiconductor material portion of an III-V aspect ratio trapping structure. The present application also relates to a method of forming such a fuse structure.
III-V compound semiconductor material co-integration is one technology option for future complementary metal oxide semiconductor (CMOS) nodes. III-V compound semiconductor materials typically require an aspect ratio trapping process to reduce defect levels to a reasonable number to manufacture high performance semiconductor devices. Fuses are used in a variety of circuit applications, also in III-V compound semiconductor material containing circuits. A fuse is a structure that can be blown in accordance with a suitable electrical current. For example, an electrical current is provided through a fuse to eventually cause the fuse to blow and create an opening circuit. It is highly desirable to fabricate on-chip fuses during CMOS fabrication to minimize process cost and improve system integration.